EngineerExperiences

Part 7 of 10 TMS320F28379DC2000Dual-CoreCCS

Synchronized Dual-Core Flashing

Programming both cores of the TMS320F28379D requires a carefully choreographed sequence across host software, CPU1, and CPU2.

Six step dual-core flash sequence from the host flasher to verification and reset 1. Host machine serial_flash_programmer 2. CPU1 RAM CPU1 flash kernel downloaded over SCI and started 3. Shared message RAM CPU2 flash kernel staged by CPU1 4. CPU2 RAM CPU2 booted by the IPC interrupt 5. Program flash CPU1 then CPU2 application, bank 0 or bank 1 6. Verify and reset kernel finishes and the core reboots
The order matters: CPU1 must already be running before it can stage and boot CPU2.

Flashing Automation Scripts

The repository includes dedicated automation scripts under TI/scripts/:

  • serial_flash_bank0.sh: flashes the bank 0 kernel and application images with the host flasher.
  • serial_flash_bank1.sh: flashes the alternate bank 1 images, leaving the running bank untouched.
  • bank_change_flash.py: sends an eight-byte bank-change command frame to the device over serial.