EngineerExperiences
On this page

Part 3 of 10 TMS320F28379DC2000Dual-CoreCCS

System Architecture

The Texas Instruments TMS320F28379D Delfino™ is a dual-core 32-bit C28x microcontroller. This project programmes it over a single serial link: the host talks to CPU1, and CPU1 brings up CPU2.

Block diagram

Host flasher reaching CPU1 over SCI and CPU1 handing over to CPU2 through IPC Host PC serial_flash_programmer: C++, CMake or Visual Studio SCI-A serial boot, ASCII SCI8, 9600 baud by default TMS320F28379D CPU1: C28x, 200 MHz receives the CPU1 flash kernel runs it from RAM, then receives its application payload IPC CPU2: C28x, 200 MHz boots on the IPC interrupt programmes its own sectors IPC_BOOT_STS, IPC_COMMAND On-chip flash: 1024 KB in two banks Bank 0 (sectors A–N) runs · Bank 1 stages the next image
The host only ever talks to CPU1; CPU2 is unreachable over SCI and is started through the IPC handshake.

Core processing engines

  • CPU1 and CPU2: two independent 200 MHz C28x 32-bit cores.
  • Trigonometric math units (TMU): hardware sine, cosine, arctan and 1/x.
  • VCU-II: Viterbi, complex-math and CRC accelerators.
  • Control law accelerators (CLA): two 32-bit floating-point co-processors running asynchronously.

Memory architecture and flash banks

The device carries 1024 KB of onboard flash in two physical banks, which is what makes a live update possible:

BankPartitionRole
Bank 0sectors A to Nthe bank the device executes from
Bank 1mirror partitionholds the staged image during a live update

A new image is written to the inactive bank while the active core keeps running, and the device switches banks on the next reset. See Hardware for the device resources, and Synchronized dual-core flashing for the switch itself.

Inter-processor communication (IPC)

CPU2 has no external SCI boot pins, so the host flasher cannot reach it directly. CPU1 coordinates:

  1. CPU1 receives the kernel and the application binaries over SCI-A.
  2. CPU1 copies the CPU2 flash kernel into the shared message RAM using the IPC registers.
  3. CPU1 raises an IPC interrupt, and CPU2 boots and programmes its own sectors.